The article by L Gaben et al. “Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities,” ECS Transactions, Vol. 72. No. 4, 2016, page 43, describes a method of forming two all-around gate transistors by a sacrificial gate method where the silicon channels are formed before the gate manufacturing. FIGS. 1A to 1G and 2A illustrate steps of the method described in the Gaben et al. article. FIGS. 1A, 1C, and 1E to 1G are cross-section views. FIGS. 1B and 1D are perspective cross-section views. FIG. 2A is a top view of the structure of FIG. 1A.
At the step of FIGS. 1A and 2A, a substrate 1 is successively covered with a silicon-germanium layer 3, with a silicon layer 5, with a SiGe layer 7, and with a silicon layer 9. Layers 3, 5, 7, and 9 are then etched in a strip 11 illustrated in FIG. 2A. Strip 11 extends between two pads 13 and 15 and has a width smaller than that of pads 13 and 15. After this, a wet selective etching of SiGe is carried out. The etching time is provided, on the one hand, to remove all the SiGe between silicon bars 17 and 19 extending between pads 13 and 15 and, on the other hand, to keep a portion 25 of SiGe layer 3 and a portion 27 of SiGe layer 7 in each pad. Bars 17 and 19 are thus suspended above substrate 1 and held by pads 13 and 15.
At the step of FIG. 1B, it is started by depositing a hydrogen silsesquioxane (HSQ) resin. The layer covers the structure and fills the space between bars 17 and 19 and under lower bar 17. A lithography of this layer is then carried out, to obtain two sacrificial gates 30. Each sacrificial gate 30 extends vertically from the substrate while surrounding a portion of each of bars 17 and 19. To achieve this, the portions of HSQ resin corresponding to sacrificial gates 30 are subjected to an ultraviolet radiation or to an electron beam running through bars 17 and 19, and are turned into silicon oxide.
At the step of FIG. 1C, an insulating layer has been conformally deposited. The material of this layer fills spaces 32 between bars 17 and 19 and between substrate 1 and bar 17. A selective anisotropic etching is then performed to remove the portions of this layer which are horizontal and non-covered. Spacers 34 are thus kept on the sides of each sacrificial gate 30 and the portions of the material filling spacers 32 are kept.
At the step of FIG. 1D, all the elements located on substrate 1 are removed by etching, except for sacrificial gates 30, spacers 34, and the elements covered with sacrificial gates 30 and with spacers 34. The remaining portions of bars 17 and 19 are the future channel regions, respectively 40 and 41, of the transistors. On either side of each of sacrificial gates 30, insulating portions 34′ which continue spacers 34 between channel regions 40 and 41 and between regions 40 and the substrate have thus been formed. Each sacrificial gate 30 and the spacers 34, 34′ on its sides are thus crossed by channel regions 40 and 41. Channel regions 40 and 41 come up to the sides of spacers 34, 34′.
At the step of FIG. 1E, a selective epitaxy is performed. The silicon grows from the exposed portions of channel regions 40 and 41 as well as from substrate 1. Two drain-source areas 42 on either side of the two sacrificial gates 30 and a drain-source area 44 between the sacrificial gates are thus formed. The obtained drain-source areas 42 and 44 rest on substrate 1.
At the step of FIG. 1F, sacrificial gates 30 are entirely removed by selective wet etching. The portions of sacrificial gates 30 located between regions 40 and 41 and under region 40 are removed. Channel regions 40 and 41 are then suspended above substrate 1.
At the step of FIG. 1G, insulated gates 50 are formed at the locations of the sacrificial gates. To achieve this, a gate insulator layer 52 of high permittivity which covers the portions of substrate 1 and channel regions 40 and 41 located at these locations is first deposited. The rest of the locations of the sacrificial gates are then filled with a conductive material forming gates 50.
Two transistors, each comprising two channel regions 40 and 41 surrounded with an insulated gate 50 and two drain-source areas 42 and 44 on either side of insulated gate 50, have thus been obtained. At a subsequent step, drain or source contacts 56 with areas 42, a drain or source contact 57 with area 44, and gate contacts 58, are formed.
In transistors obtained by the method previously described in relation with FIGS. 1A to 1G, the drain-source areas rest, at least partly, directly on the substrate. When the substrate is a solid semiconductor, conduction may occur through the substrate between the drain-source areas. To limit the conduction of this parasitic channel, it may be provided for a portion of the substrate located under the suspended channels to be doped with a conductivity type different from that of the drain-source areas to increase the threshold voltage of the parasitic transistor. Despite this precaution, when a gate voltage is applied to one of the transistors between contact 58 and contact 56 or 57 to turn on the transistor, leakage currents may flow through the substrate portion located under insulated gate 50.
The transistors thus obtained raise various operation issues when substrate 1 is a solid semiconductor material, called “bulk”, and more generally when substrate 1 is not covered with a layer of insulator such as the insulator of a SOI-type structure (Silicon On Insulator).
There is according a need in the art to address the foregoing concerns.